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Low power asynchronous counter and method
Low power asynchronous counter and method
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机译:低功耗异步计数器和方法
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摘要
Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal outputs of the plurality of flip-flops are sampled by successively delayed versions of a reference signal. Further design techniques for generating successively delayed versions of the reference signal are disclosed. In an exemplary embodiment, the asynchronous counting techniques may be utilized in a high-speed counter for a digital-phase locked loop (DPLL).
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