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System and Method for Offsetting The Data Buffer Latency of a Device Implementing a JEDEC Standard DDR-4 LRDIMM Chipset
System and Method for Offsetting The Data Buffer Latency of a Device Implementing a JEDEC Standard DDR-4 LRDIMM Chipset
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机译:用于抵消实现JEDEC标准DDR-4 LRDIMM芯片组的设备的数据缓冲区延迟的系统和方法
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摘要
A system and method for offsetting the data buffer latency in a CPIO device having a JEDEC standard DDR-4 LRDIMM chipset as the front end is disclosed. According to one embodiment, a CPIO ASIC provides variable timing control for its DDR-4 LRDIMM interface such that propagation delay of the data buffers can be offset by the CPIO ASIC, allowing the CPIO LRDIMM to be timing compatible with an RDIMM.
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