CLOCK TREE UNIT CELL CIRCUIT, CLOCK TREE, AND APPARATUS

摘要

A clock tree unit cell circuit includes a first input terminal configured to receive a clock signal from an upstream side of a clock tree; a first output terminal configured to output a clock signal to a downstream side of the clock tree; a second input terminal configured to receive a standby signal from the upstream side of the clock tree; a third input terminal configured to receive a standby signal from the downstream side of the clock tree; a logic circuit configured to perform a predetermined logical operation on the clock signal inputted to the first input terminal and output the clock signal to the first output terminal; and a control circuit that is connected to the second input terminal, the third input terminal, and an output control terminal of the logic circuit.