首页> 外国专利> METHODS FOR REDUCING MEMORY SPACE IN SEQUENTIAL OPERATIONS USING DIRECTED ACYCLIC GRAPHS

METHODS FOR REDUCING MEMORY SPACE IN SEQUENTIAL OPERATIONS USING DIRECTED ACYCLIC GRAPHS

机译:使用直接循环图减少序贯运算中的存储空间的方法

摘要

Various disclosed embodiments are directed to methods and systems for reducing memory space in sequential computer-implemented operations. The method includes generating a directed acyclic graph (DAG) having a plurality of vertices and directed edges, wherein each edge connects a predecessor vertex to a successor vertex. Each vertex represents one of the computer-implemented operations and each directed edge represents output data generated by the operations. The method includes merging one of the predecessor vertex with one of the successor vertex by combining the operations of the predecessor vertex and the successor vertex if the predecessor and successor vertices are connected by a directed edge and there is only one directed edge originating from the predecessor vertex. The merger of the predecessor and the successor vertices reduces the number of directed edges in the DAG, resulting in a reduction of intermediate buffer memory required to store the output data.
机译:各种公开的实施例针对用于在顺序计算机实现的操作中减少存储器空间的方法和系统。该方法包括生成具有多个顶点和有向边的有向无环图(DAG),其中每个边将前任顶点连接到后继顶点。每个顶点表示计算机执行的操作之一,每个有向边表示由这些操作生成的输出数据。该方法包括:如果前导顶点和后继顶点通过有向边连接并且只有一个源自前任顶点的有向边,则通过合并前任顶点和后继顶点的操作来合并前任顶点之一和后继顶点之一。顶点。前导顶点与后继顶点的合并减少了DAG中有向边的数量,从而减少了存储输出数据所需的中间缓冲存储器。

著录项

  • 公开/公告号US2015212933A1

    专利类型

  • 公开/公告日2015-07-30

    原文格式PDF

  • 申请/专利权人 NVIDIA CORPORATION;

    申请/专利号US201414165789

  • 发明设计人 VINOD GROVER;MAHESH RAVISHANKAR;

    申请日2014-01-28

  • 分类号G06F12/02;G06T1/60;

  • 国家 US

  • 入库时间 2022-08-21 15:23:47

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