System and method for selectively managing a branch target address cache of a multiple-stage predictor

摘要

A multiple stage branch prediction system including a branch target address cache (BTAC) and a branch predictor circuit is disclosed. The BTAC is configured to store a BTAC entry. The branch predictor circuit is configured to store state information. The branch predictor circuit utilizes the state information to predict the direction of a branch instruction and to manage the BTAC entry based on the stored state information in response to actual resolution of the branch instruction.