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Adaptive architecture in a channel detector for NAND flash channels
Adaptive architecture in a channel detector for NAND flash channels
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机译:通道检测器中用于NAND闪存通道的自适应架构
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摘要
An apparatus comprising a memory configured to store data and a controller. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller is configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether the read is successful, (iii) if the read is not successful, perform a plurality of reads with a varying value of the threshold voltage, (iv) read a calibration value from a look-up table based on the plurality of reads and (v) set the threshold value in response to the calibration value.
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