首页> 外国专利> Phase-to-amplitude converter for direct digital synthesizer (DDS) with reduced AND and reconstructed ADD logic arrays

Phase-to-amplitude converter for direct digital synthesizer (DDS) with reduced AND and reconstructed ADD logic arrays

机译:具有减少的AND和重构的ADD逻辑阵列的直接数字合成器(DDS)的相幅转换器

摘要

A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.
机译:用于直接数字合成器(DDS)的正弦波发生器将数字相位输入转换为数字正弦波输出。正弦值和斜率存储在只读存储器(ROM)中,用于存储第一象限中的上位相位粗位。象限折叠器和分相器反射并反转第一个象限的值,以生成所有四个象限的幅度。每个正弦值和斜率都存储在较低相位位的范围内。 Delta位将上,下相位位分开。 Delta有条件地反转低相位位,正弦值和最终极性。精简的AND逻辑阵列将斜率乘以条件反转的较低相位位。然后,重建的ADD逻辑阵列将条件反转的正弦值相加。将条件反转的极性相加以生成最终的正弦值。基于Delta位的条件反转可以简化正弦生成逻辑。

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