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Data processing unit and signal receiver including the data processing unit

机译:数据处理单元和包括该数据处理单元的信号接收器

摘要

The processing unit has clock and data recovery circuit. A processor circuit is connected to clock and data recovery circuit (16), such that processor circuit is arranged to calculate mean and variance overtime of numerical input signal of numerically controlled oscillator (25) so as to determine coherence of data signal if calculated mean and variance are below predefined coherence threshold. The reset of receiver is performed if calculated mean or variance of numerical input signal of numerically controlled oscillator is above predefined coherence threshold. An independent claim is included for signal receiver.
机译:处理单元具有时钟和数据恢复电路。处理器电路连接至时钟和数据恢复电路(16),使得处理器电路被布置为计算数控振荡器(25)的数字输入信号的均值和方差随时间变化,从而确定计算出的均值和数据的相干性。方差低于预定义的相干阈值。如果数控振荡器的数字输入信号的计算平均值或方差高于预定义的相干阈值,则执行接收器的重置。信号接收器包含独立声明。

著录项

  • 公开/公告号EP2445138B1

    专利类型

  • 公开/公告日2015-07-15

    原文格式PDF

  • 申请/专利权人 THE SWATCH GROUP RESEARCH AND DEVELOPMENT LTD.;

    申请/专利号EP20100188479

  • 发明设计人 CASAGRANDE ARNAUD;

    申请日2010-10-22

  • 分类号H04L7/033;H03L7/08;H03L7/085;

  • 国家 EP

  • 入库时间 2022-08-21 15:07:40

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