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Three-wire three-level digital interface

机译:三线三级数字接口

摘要

A receiver (100) for a three-wire digital interface, comprises a first resistive element (R1) coupled between a first input terminal (A) and a first junction node (JA), a second resistive element (R2) coupled between a second input terminal (B) and a second junction node (JB), and a third resistive element (R3) coupled between a third input terminal (C) and a third junction node (JC). A network (70) comprising first second and third network terminals (71, 72, 73) is coupled to, respectively, first, second and third junction nodes (JA, JB, JC). The network has substantially the same impedance between all pairs of the first, second and third network terminals. A first comparator (C1) has a non-inverting input (10) coupled to the first input terminal (A), an inverting input (12) coupled to the second junction node (JB), and an output (14) coupled to a first output terminal (AJ). A second comparator (C2) has a non-inverting input (20) coupled to the first input terminal (A), an inverting input (22) coupled to the third junction node (JC), and an output (24) coupled to a second output terminal (AK). A third comparator (C3) has a non-inverting input (30) coupled to the second input terminal (B), an inverting input (32) coupled to the third junction node (JC), and an output (34) coupled to a third output terminal (BJ). A fourth comparator (C4) has a non-inverting input (40) coupled to the second input terminal (B), an inverting input (42) coupled to the first junction node (JA), and an output (44) coupled to a fourth output terminal (BK). A fifth comparator (C5) has a non-inverting input (50) coupled to the third input terminal (C), an inverting input (52) coupled to the first junction node (JA), and an output (54) coupled to a fifth output terminal (CJ). A sixth comparator (C6) has a non-inverting input (60) coupled to the third input terminal (C), an inverting input (62) coupled to the second junction node (JB), and an output (64) coupled to a sixth output terminal (CK).
机译:用于三线数字接口的接收器(100),包括耦合在第一输入端子(A)和第一结节点(JA)之间的第一电阻元件(R1),耦合在第二输入端子(JA)之间的第二电阻元件(R2)输入端(B)和第二结点(JB),以及耦合在第三输入端(C)和第三结点(JC)之间的第三电阻元件(R3)。包括第一第二和第三网络终端(71、72、73)的网络(70)分别耦合到第一,第二和第三结点节点(JA,JB,JC)。该网络在第一,第二和第三网络端子的所有对之间具有基本相同的阻抗。第一比较器(C1)具有连接到第一输入端子(A)的同相输入(10),连接到第二结点(JB)的反相输入(12)和连接到APN的输出(14)第一输出端子(AJ)。第二比较器(C2)具有连接到第一输入端子(A)的同相输入(20),连接到第三结点(JC)的反相输入(22)和连接到A3的输出(24)第二个输出端子(AK)。第三比较器(C3)具有耦合到第二输入端子(B)的同相输入(30),耦合到第三结点(JC)的反相输入(32)和耦合到第三结点的输出(34)。第三输出端子(BJ)。第四比较器(C4)具有耦合到第二输入端子(B)的同相输入(40),耦合到第一结点(JA)的反相输入(42)和耦合到第二结点(JA)的输出(44)。第四输出端子(BK)。第五比较器(C5)具有耦合到第三输入端(C)的同相输入(50),耦合到第一结点(JA)的反相输入(52)和耦合到第一结点(JA)的输出(54)。第五个输出端子(CJ)。第六比较器(C6)具有耦合到第三输入端(C)的同相输入(60),耦合到第二结点(JB)的反相输入(62)和耦合到第二结点(J)的输出(64)。第六输出端子(CK)。

著录项

  • 公开/公告号EP2816765A1

    专利类型

  • 公开/公告日2014-12-24

    原文格式PDF

  • 申请/专利权人 ST-ERICSSON SA;

    申请/专利号EP20130172355

  • 发明设计人 KOLI KIMMO;

    申请日2013-06-17

  • 分类号H04L25/02;

  • 国家 EP

  • 入库时间 2022-08-21 15:04:27

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