A method for testing an Arithmetic logic unit of a flight control system

摘要

An arithmetic logic unit (ALU) (100) for use within a flight control system is provided. The ALU (100) comprises a first register (110) configured to receive a first operand, a second register (111) configured to receive a second operand, and an adder (130) coupled to the first register (110) and the second register (111). The adder (130) is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.