METHOD AND APPARATUS FOR SAVING PROCESSOR ARCHITECTURAL STATE IN CACHE HIERARCHY

摘要

Processor 105 stores data for use by the first processing unit (110, 115) and being associated with the first processing unit, the first processing unit to be used during normal operation of the first processing unit, possible to operate, a first level cache (220). The first processing unit is power-down signal in response to receiving the first structural state data for the first processing unit to the first level cache is operable to store (240, 250, 260). Level cache (220, 230) comprising a layer of a method for controlling power to the processor 105, a power-down the first processing of the processor to the first level 220 of the caching hierarchy in response to receiving the signal unit (110, 115) data for the first structural state (240, 250, 260) storing the first level and the first processing unit is power of the cache hierarchy-down before, the cache hierarchy of the 1 includes the first step of flushing the contents of the first level comprises a structural state data on the lower level 230. ;