- Layout method of semiconductor memory device implementing full-VDD bitline precharge scheme usig asymmetric sense amplifier

摘要

The present invention provides a full sense amplifier using an asymmetric-bit implementation of the power-supply voltage line pre-charge car scheme which it is described with respect to the alignment of the semiconductor memory device. Asymmetric sense amplifier, the third and the cross-connect is connected to the first current source to the bit line and the first and second transistors that are cross-connected to the complementary bit line, a second current source connected to the bit line and the complementary bit line, 4 includes the transistor, the current driving capability of the first and the fourth transistor is set to be larger than the current driving capability of the second and third transistors. Placing a semiconductor memory device, the current driving capability is placed adjacent to the small third transistor and the first memory cell, the current driving capability is disposed adjacent the small second transistor to a second memory cell. The current driving capability larger transistors are arranged to have the active regions separated by the number obtained by dividing the width of the small width of the transistor, the current driving capability. ; asymmetrical sense amplifiers, sensing speed, threshold voltage mismatch, full-power car bit line pre-charge voltage,