Dividing work among multiple graphics pipelines using a super-tiling technique

摘要

A graphics processing circuit in a processor chip, comprising: at least two graphics pipelines in the chip, each pipeline operative independently to process data in a respective dedicated tile of a set of tiles in a repeating tile pattern that includes a horizontally and vertically repeating pattern of non-square regions; and a memory controller in the chip coupled to the at least two graphics pipelines, operative to transfer pixel data between each of the first pipeline and the second pipeline and a graphics memory shared between the at least two graphics pipelines.