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VERIFICATION SEQUENCE DETERMINING PROGRAM, VERIFICATION SEQUENCE DETERMINING METHOD, AND VERIFICATION SEQUENCE DETERMINING DEVICE

机译:验证序列确定程序,验证序列确定方法和验证序列确定设备

摘要

PROBLEM TO BE SOLVED: To accurately determine the sequence of tests for verification.;SOLUTION: A verification sequence determining program causes a computer to execute processing to calculate for each test a priority level representing the relative priority of logic verification on the basis of predictive information predicting for each module involved in logic verification the probability of trouble occurrence and the comprehensiveness of tests to a module when a test for logic verification is performed. Also, the verification sequence determining program causes the computer to execute processing to output, on the basis of a priority level calculated for each test, the sequence of verification to be conducted on tests.;SELECTED DRAWING: Figure 2;COPYRIGHT: (C)2016,JPO&INPIT
机译:解决的问题:准确确定验证的测试顺序;解决方案:验证顺序确定程序使计算机执行处理,以针对每个测试计算优先级,该优先级表示基于预测信息的逻辑验证的相对优先级在执行逻辑验证测试时,为逻辑验证涉及的每个模块预测故障发生的可能性以及对模块的测试全面性。同样,验证顺序确定程序使计算机执行处理,以基于为每个测试计算的优先级输出要对测试进行的验证顺序。;选择的图纸:图2;版权:(C) 2016,日本特许厅

著录项

  • 公开/公告号JP2016091062A

    专利类型

  • 公开/公告日2016-05-23

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20140220815

  • 发明设计人 KANAZAWA YUJI;PARISI MATTHEW;

    申请日2014-10-29

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 14:46:52

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