BUS BRIDGE AND BUS BRIDGE GROUP

摘要

PROBLEM TO BE SOLVED: To obtain a bus bridge that can alleviate a processing content upon processing of reading data between different bus specifications, and can simplify a device configuration.SOLUTION: A decoder 20 is configured to generate a memory access signal S20A for a memory 400 to be connected to a PCIe bus 32, using a data correspondence table or data conversion formula in between an AXI bus specification and a PCIe bus specification on the basis of a first reading control signal (AD1, BL1 and BS1); and output the memory access signal S20A to the memory 400 via the PCIe bus 32. In the memory access signal S20A, an address AD2 of the PCIe bus specification, burst size BS2 thereof, burst length BL2 thereof, first byte enable FB3 and last byte enable LB3 thereof are included as control information.SELECTED DRAWING: Figure 2