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SYNCHRONIZATION ESTABLISHMENT SYSTEM AND SYNCHRONIZATION ESTABLISHMENT METHOD

机译:同步建立系统及同步建立方法

摘要

PROBLEM TO BE SOLVED: To provide a synchronization establishment system capable of minimizing data error, without increasing the control load or circuit scale, even if the system of a main device circuit is switched at a desired timing, in a synchronization establishment system where the main device circuit is duplicated.SOLUTION: In a synchronization establishment system 10, control circuits 20, 30 include clock generation means 21, 31, frame head generation means 22, 32 for generating frame heads, and adjustment signal generation means 23, 33 for generating adjustment signals, at predetermined intervals, by using a reference clock, and outputting the adjustment signals while inserting to predetermined positions of the frame head, respectively. A plurality of interface circuits 40 synchronize with the control circuits connected therewith, by using a bit counter that is counted up every time when a reference clock is inputted and cleared when the adjustment signal is inputted, and a ch counter that is counted up every time when the adjustment signal is inputted and cleared when the frame head is inputted.SELECTED DRAWING: Figure 1
机译:解决的问题:提供一种同步建立系统,该同步建立系统在同步建立系统中,即使主设备电路的系统在期望的定时被切换,也能够在不增加控制负荷或电路规模的情况下最小化数据错误。解决方案:在同步建立系统10中,控制电路20、30包括时钟生成装置21、31,用于生成帧头的帧头生成装置22、32和用于生成调整的调整信号生成装置23、33。通过使用参考时钟以预定的间隔发送信号,并在分别插入到帧头的预定位置的同时输出调整信号。多个接口电路40通过使用每次输入参考时钟时计数的位计数器和输入调整信号时清除的位计数器,以及每次计数的ch计数器,使与其连接的控制电路同步。当输入调节信号时,当输入帧头时将其清除。选择的绘图:图1

著录项

  • 公开/公告号JP2016052025A

    专利类型

  • 公开/公告日2016-04-11

    原文格式PDF

  • 申请/专利权人 NEC ENGINEERING LTD;

    申请/专利号JP20140176925

  • 发明设计人 YAMAMOTO MOTOMITSU;

    申请日2014-09-01

  • 分类号H04L7/02;

  • 国家 JP

  • 入库时间 2022-08-21 14:46:07

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