AN EXTENSIBLE AND CONFIGURABLE LOGIC ELEMENT, AND AN FPGA DEVICE

摘要

An extensible and configurable logic element, wherein the logic element includes: multiple logic parcels, each logic parcel includes two logic cells; each logic cell includes seven inputs, three outputs, an addition carry input, an addition carry output, a six-input and two-output look-up table, a one bit full adder, a first register, and a second register; wherein, the first register stores a signal output by the first output of the look-up table or a carry signal of the full adder according to the configuration; the second register stores a signal output by the second output of the look-up table or an output signal of the full adder according to the configuration; the addition carry output in the current logic cell is connected to the addition carry input in the higher logic cell of the current logic cell, including an addition carry chain in the logic element.