TECHNOLOGIES FOR HIGH-SPEED PCS SUPPORTING FEC BLOCK SYNCHRONIZATION WITH ALIGNMENT MARKERS

摘要

Technologies for high-speed data transmission include a network port logic having one or more communication lanes coupled to a forward error correction (FEC) sublayer and a physical coding sublayer (PCS). To transmit data, the PCS encodes the data to be transmitted into encoded data blocks using a 66b/64b line code and inserts alignment marker blocks after every 16,383 encoded data blocks. The FEC encodes the encoded data blocks into 80-block FEC codewords starting at a predefined offset from an alignment marker. Thus, each alignment marker is at one of five predefined offsets from the beginning of an FEC codeword. Each alignment marker may include a unique block type field usable with FEC encoding. The PCS may include one or more logical lanes, each operating at 25 Gb/s. Embodiments of the network port logic may include a single PCS lane or sixteen PCS lanes. Other embodiments are described and claimed.