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Autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency

机译:可自动配置的锁相环,可自动保持恒定的阻尼因子,并将环路带宽调整为参考频率的恒定比率

摘要

A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.
机译:锁相环(PLL)包括一个状态机,该状态机被编程为自动产生一组控制信号以选择电荷泵电流并积分电容值以自动调整PLL的环路带宽。电荷泵DAC产生一个由状态机控制信号控制的幅度的电荷泵电流。积分器对电荷泵输出电流进行积分,以产生积分的电荷泵输出信号。积分器具有多个电容器,这些电容器通过来自状态机的控制信号可切换地选择,以产生积分电容值。压控振荡器(VCO)响应于集成的电荷泵输出信号产生PLL输出频率。

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