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Transceiver circuitry with summation node common mode droop reduction
Transceiver circuitry with summation node common mode droop reduction
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机译:具有求和节点共模下垂减少功能的收发器电路
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摘要
An integrated circuit having transceiver circuitry is provided. The transceiver circuitry may include an equalization circuit such as a decision feedback equalizer (DFE). The DFE may include a variable gain amplifier (VGA) that is coupled to a summation node circuit and a digital sampler. The DFE may also include an operational amplifier that is coupled in a negative feedback loop and that provides a controlled power supply voltage to the VGA so that the VGA is able to provide a stable common mode output voltage to the digital sampler. The operational amplifier may be a self-biased operational amplifier with an output stage that includes miller compensation circuitry for enhanced stability.
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