首页> 外国专利> Defect analysis system for error impact reduction

Defect analysis system for error impact reduction

机译:缺陷分析系统,减少错误影响

摘要

An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to analyze a first set of data associated with a plurality of data sources. Analyzing the first set of data associated with the plurality of data sources determines a plurality of relationships among the first set of data. The processor is configured to store indications of the plurality of relationships among the first set of data. An indication of a relationship indicates a possible software defect. The processor is configured to generate rules based, at least in part, on the first set of data associated with a plurality of data sources. A rule indicates a possible software defect.
机译:一种设备,包括网络接口,存储器和处理器。处理器与网络接口和内存耦合。处理器被配置为分析与多个数据源相关联的第一组数据。分析与多个数据源相关联的第一数据集确定第一数据集之间的多个关系。处理器被配置为存储第一组数据之间的多个关系的指示。关系的指示指示可能的软件缺陷。处理器被配置为至少部分地基于与多个数据源相关联的第一组数据来生成规则。规则指示可能的软件缺陷。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号