Methods and apparatus for estimating and compensating for nonlinearity errors

摘要

An estimation unit (30, 30a-c) to estimate an error of non-linearity of a conversion circuit (10), wherein the conversion circuit is adapted to receive an input signal in continuous time and outputting a signal digital output, wherein the input signal in continuous time is band-limited to essentially one band angular frequency having a lower limit (w1) and an upper limit (w2), where w1 (L-1) p / T, w2 Lp / T, L is a positive integer and T is a sampling period of the conversion circuit, the estimation unit (30, 30a-c) comprising: an input port (32, 32a-c ) for receiving a digital input signal having a first sampling rate 1 / T, in which the digital input signal is the digital output signal conversion circuit (10); and an output port (34, 34a-c) for outputting a digital signal estimated error that the first sampling rate, wherein the digital signal estimated error is an estimate of the nonlinearity error conversion circuit ( 10), wherein the estimation unit comprises a branch for each p_k, wherein p_k is an integer into a set of integers, k is an integer in a range 1 = k = N and p_k is greater than or equal to 2, each branch comprising: - a first unit linear filter (100-k) to generate a first signal (s1 (n)) as a linear function of the digital input signal; - one interpolation unit (105-k) to interpolate the first signal (s1 (n)) to generate a second signal (s2 (m)) having a second sampling rate which is a factor L · highest R_k that first sampling rate, where R_k is a value selected so that L · R_k = T · w2 · p_k / w; - a unit of nonlinearity (110-k) to generate a third signal (s3 (m)) as said second signal (s2 (m)) to the power p_k; and - a second unit linear filter (115-k) to generate a signal component of digital estimated error based on the third signal (s3 (m)), wherein said component has the first sampling rate, where the filter coefficients of the linear filter units first and second are set such that the estimation unit is a model of discrete-time conversion circuit and mimics the behavior of the conversion circuit with a desired accuracy; and an adder circuit (117) for generating the digital signal estimated error such as the sum of all said components of said branches.