System and method for optimizing word widths digital circuits using bit-true simulations

摘要

System and method for optimizing word widths digital circuits using bit-true simulations. The system comprises a model of the target circuit (5) with limiting circuits (7) modifying the value of the signals whose widths word is to be optimized. Each limiter circuit (7) generates an output limiting logic level accuracy and / or effective range of the value of an input (NUM {sub, i}) according to an instruction of control precision and / or effective range (10 { sub, i}) received. The model of the target circuit (5) can be implemented in hardware circuitry of a PLD (2) or by software in a processor (8). Each limiter circuit (7) is normally located at the input and / or output of a bitwise arithmetic operator (9) or an arithmetic logic unit (19). # Reduces runtimes process optimization by simulation bit -true, avoiding PLD reconfiguration or emulation word widths using software instructions.