Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating (810) hardware latency for a hardware accelerator implementation of the selected partition, scheduling (815) the selected partition using the hardware latency generating hardware partition latency information, and compiling (820) an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed (825) generating software latency information. A design performance for the design is determined (830) through combining the hardware partition latency information with the software latency information.
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