Devices and related systems and methods for determining a cache hit / miss of aliased addresses in virtual-tagged cache (s) are disclosed. In one embodiment, a virtual aliasing cache hit / miss detector for the VIVT cache is provided. The detector includes a TLB configured to receive a first virtual address and a second virtual address from a VIVT cache resulting from an indexed read into a VIVT cache based on a first virtual address. The TLB is further configured to generate first and second physical addresses, respectively, that are translated from the first and second virtual addresses. The detector further includes a comparator configured to receive the first and second physical addresses and to achieve the generation of the aliased cache hit / miss indicator based on the comparison of the first and second physical addresses. In this way, the virtual aliasing cache hit / miss detector correctly generates cache hits and cache misses even in the presence of aliased addressing.
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