LOW POWER WIDEBAND NON-COHERENT BPSK DEMODULATOR TO ALIGN THE PHASE OF SIDEBAND COMPARATORS, USING 1ST ORDER SIDEBAND FILTERS WITH PHASE 180 DEGREE ALIGNMENT

摘要

An embodiment of the present invention is directed to a low power wideband asynchronous BPSK demodulation method and the circuit thereof. In the constitution of a BPSK demodulation circuit, provided is a low power wideband asynchronous BPSK phase shift demodulation circuit, comprising: a sideband digital separating part configured to separate a demodulated signal into a first high pass filter and a first low pass filer whose cut-off frequencies are carrier frequencies and into an upper sideband and a lower sideband, and for the digitalization, to minimize a jitter while having a digital output of the lower sideband comparator as a constant phase and a digital output of the upper sideband comparator as a negative phase; a lower sideband signal delay and a phase detecting clock part for generating a signal that delays the lower sideband digital signal as much as /2 of a carrier frequency, and a symbol edge signal which aligns the phase difference of the delayed digital signal of the lower sideband and the digital signal of the upper sideband at 180 degrees and comprises a glitch to be used as a detecting clock for data demodulation; a data demodulator for demodulating digital data by using the delayed lower sideband digital signal and the symbol edge signal from which the glitch is removed through a deglitch filter; and a data clock restoration part for generating a data clock by using the delayed lower sideband digital signal and the data signal. The present invention is designed to provide a demodulation mode which can also be applied to a high speed digital communication device and a mobile communication device that require lower power consumption, and thus it is appropriate to implement system on chip (SoC), and thus provides excellent convenience and high economical efficiency.