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PHASE GENERATOR BASED ON DELAY LOCK LOOP CIRCUIT AND DELAY LOCKING METHOD THEREOF

机译:基于延时锁定回路的相位发生器及其延时锁定方法

摘要

The present invention relates to a phase generator based on a delay locked loop circuit and a phase generating method capable of preventing locking errors while realizing broadband by placing a delay timing on an optimal band depending on the result of comparing an input clock and an output clock. The phase generator comprises: a delay control unit for producing and outputting an oscillating control voltage based on the result of comparing a phase of an outer standard clock and feedback clock signals to the frequency; a course setting unit for setting a band region for locking errors based on preventing conditions; a regulator for adjusting a set voltage level corresponding to the band region of the course setting unit and outputting the same; and a voltage control delay line for converting and outputting a phase of at least one output clock and a voltage level based on the set voltage of the regulator and control voltage of the delay control unit.
机译:本发明涉及一种基于延迟锁定环电路的相位产生器和一种相位产生方法,其能够根据输入时钟和输出时钟的比较结果,通过将延迟定时置于最佳频带上,从而在实现宽带的同时防止锁定错误。 。相位发生器包括:延迟控制单元,用于基于将外部标准时钟和反馈时钟信号的相位与频率进行比较的结果来产生和输出振荡控制电压;以及路线设置单元,用于基于防止条件来设置用于锁定错误的带区域;调节器,用于调节与路线设定单元的频带区域相对应的设定电压电平并输出。电压控制延迟线,用于基于调节器的设定电压和延迟控制单元的控制电压来转换并输出至少一个输出时钟的相位和电压电平。

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