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A data transmission system with a reduced power consumption, a method and transmission circuit

机译:具有降低的功耗的数据传输系统,方法和传输电路

摘要

The transmission circuit, withan encoder (400, 905), which is coupled to a data input,the encoder (400, 905) circuits, in order at the data input data words in the code words with a minimum number of the occurrence of a particular state, wherein the code word bits is longer than the data word,the encoder (400, 905) a weighting computer and a plurality of logic blocks (410, 411, 412, 413) comprises,the weighting computer (405) is coupled to the data input and circuits, a count value of the number of times that of the particular condition occurs in a data word, to determine and based on the count value to calculate a weighting bit, wherein, when the count value is greater than half the total number of bits in the data word is, the data word is inverted and the weighting bit is set on the specific state, and otherwise the weighting bits to the inverse of the certain state is set;wherein the plurality of logic blocks (410, 411, 412, 413) on the data input and the weighting computer (405), and wherein at each logic block to a first input of a single bit of the data word and a second input the weighting bits, which is calculated by the weighting computer, is coupled, wherein each logic block the first and second inputs, are combined one bit of the of a block of the code word, wherein the data word is inverted, if the weighting bit is set on the specific state, and wherein the code word the code block and the weighting of bits; anda transmitter (105, 910), which is coupled to the encoder, wherein the transmitter circuits, the code words in order to a transmission line (115, 915) to be fed,the transmission line (115, 915) asymmetrically over a termination with a high voltage potential is closed off, wherein the certain state on the transmission line (115, 915) is a low voltage potential.
机译:具有与数据输入端耦合的编码器(400、905)的传输电路,编码器(400、905)电路按顺序在数据输入处以最小的次数出现代码字中的数据字。在特定状态下,其中码字比特比数据字长,编码器(400、905)加权计算机和多个逻辑块(410、411、412、413)包括,加权计算机(405)被耦合对于数据输入和电路,在数据字中出现特定条件次数的计数值,以确定并基于该计数值计算加权位,其中,当计数值大于一半时所述数据字中的比特总数为:将所述数据字取反,并在所述特定状态下设置所述加权位,否则设置为与所述特定状态相反的加权位;其中,所述多个逻辑块(410数据输入和加权计算机(405)上的(411、412、413),其中,在每个逻辑块上,将数据字的单个比特的第一输入和第二输入耦合到加权计算机,该加权比特是由加权计算机计算的,其中每个逻辑块将第一和第二输入组合在一起码字块的比特,其中,如果加权比特被设置在特定状态,则数据字被反转,并且其中,码字是代码块和比特的加权;发射器(105、910),其耦合到编码器,其中,发射器电路将代码字电路化,以便馈送至传输线(115、915),传输线(115、915)在终端上不对称高压电势被关闭,其中传输线(115、915)上的特定状态是低压电势。

著录项

  • 公开/公告号DE112004003153B4

    专利类型

  • 公开/公告日2016-01-07

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号DE20041103153T

  • 发明设计人 OLIVER DR.-ING. KIEHL;

    申请日2004-09-30

  • 分类号H04L25/49;

  • 国家 DE

  • 入库时间 2022-08-21 14:10:22

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