首页>
外国专利>
TECHNIQUES FOR ENABLING BIT-PARALLEL WIDE STRING MATCHING WITH A SIMD REGISTER
TECHNIQUES FOR ENABLING BIT-PARALLEL WIDE STRING MATCHING WITH A SIMD REGISTER
展开▼
机译:使用SIMD寄存器实现位并行宽字符串匹配的技术
展开▼
页面导航
摘要
著录项
相似文献
摘要
Various embodiments are generally directed to overcoming limitations of vector registers in their use with bit-parallel string matching algorithms. An apparatus includes a processor element; and logic to receive a pattern comprising a first string of elements to employ in a string matching operation, instantiate a test bitmask in a first vector register of the processor element, the first vector register comprising multiple lanes, copy bit values at MSB bit positions of the multiple lanes of the first vector register to a first vector mask as a vector value, bit-shift the vector value as a scalar value, bit-shift the first vector register, employ the vector value of the first vector mask to selectively fill LSB bit positions of lanes of a second vector register of the processor element; and OR the second vector register into the first vector register. Other embodiments are described and claimed.
展开▼