Clock signal generating circuit, and clock signal generating method of clock signal generating circuit

摘要

A clock signal generating circuit (100) that generates a clock signal, the clock signal generating circuit including a clock signal generator configured to generate a reference clock signal (111); and a plurality of dividers (102, 103, 104) to which the reference clock signal (111) is to be input. A division ratio of at least one of the plurality of dividers varies based on division ratio data that defines the division ratio of the at least one of the plurality of dividers. The division ratio data represents a value that fluctuates around reference division ratio data with respect to time.