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CIRCUIT DESIGN ASSISTANCE PROGRAM, CIRCUIT DESIGN ASSISTANCE METHOD, AND INFORMATION PROCESSING DEVICE

机译:电路设计辅助程序,电路设计辅助方法和信息处理设备

摘要

PROBLEM TO BE SOLVED: To enable a designer to set constraint conditions while watching a topology image on a screen.SOLUTION: An information processing device 100 generates topology data 102 indicating the wiring state of paths p1, p2 by a symbol corresponding to a component included in the path p1 that satisfies a prescribed condition among the paths p1, p2 having a selected element that is included in a circuit 110 and nodes NO1-NO6 corresponding to each of the terminal of a component included in the path p1 and the branch point of a connection line. The information processing device 100 generates, for each of the paths p1, p2, correspondence data 113-1, 113-2 indicating a corresponding relation between the terminals of components included in the paths p1, p2 and the nodes indicated by the topology data 102. The information processing device 100 displays the generated correspondence data 113-1, 113-2, the topology data 102, and an input column 114 capable of accepting constraint data indicating constraint conditions for the paths p1, p2.SELECTED DRAWING: Figure 1
机译:解决的问题:使设计者能够在观看屏幕上的拓扑图像时设置约束条件。解决方案:信息处理设备100生成拓扑数据102,该拓扑数据102通过与所包括的组件相对应的符号来指示路径p1,p2的布线状态。在路径p1中满足预定条件的路径p1中,具有电路110中包括的选择元素的p2和与路径p1中包括的组件的每个端子和分支点相对应的节点NO1-NO6连接线。信息处理设备100针对路径p1,p2中的每一个生成对应性数据113-1、113-2,该对应性数据113-1、113-2指示路径p1,p2中包括的组件的端子与由拓扑数据102指示的节点之间的对应关系。信息处理设备100显示生成的对应数据113-1、113-2,拓扑数据102和输入列114,该输入列114能够接受表示路径p1,p2的约束条件的约束数据。

著录项

  • 公开/公告号JP2017010394A

    专利类型

  • 公开/公告日2017-01-12

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20150126915

  • 发明设计人 OKUBO RYOKO;SATO MITSURU;KUMAGAI KAZUNORI;

    申请日2015-06-24

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 14:01:57

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