首页> 外国专利> DIGITAL ANALOG CONVERSION CIRCUIT, DATA DRIVER, DISPLAY DEVICE, AND ELECTRONIC APPARATUS, AND DRIVING METHOD OF DIGITAL ANALOG CONVERSION CIRCUIT, DRIVING METHOD OF DATA DRIVER, AND DRIVING METHOD OF DISPLAY DEVICE

DIGITAL ANALOG CONVERSION CIRCUIT, DATA DRIVER, DISPLAY DEVICE, AND ELECTRONIC APPARATUS, AND DRIVING METHOD OF DIGITAL ANALOG CONVERSION CIRCUIT, DRIVING METHOD OF DATA DRIVER, AND DRIVING METHOD OF DISPLAY DEVICE

机译:数字模拟转换电路,数据驱动器,显示设备和电子设备,以及数字模拟转换电路,数据驱动器的驱动方法和显示设备的驱动方法

摘要

PROBLEM TO BE SOLVED: To provide a digital analog conversion circuit capable of reducing the variation of settling time due to correspondence of a differential pair and the voltage.SOLUTION: A digital analog conversion circuit 1020 includes a selector unit 102D for selecting a plurality of nodes from a voltage-dividing circuit according to the high-order side bit information of a digital signal and outputting a voltage, and a differential amplification unit 102F including a plurality of differential pairs to which the output voltage from the selector unit is inputted. Correspondence of the output voltage from the selector unit and the input of each differential pair of the differential amplification unit is controlled according to the bit information on the low-order side of the digital signal, and a voltage according to the digital signal is outputted. When outputting a voltage according to the digital signal, the correspondence of the output voltage from the selector unit and the input of each differential pair of the differential amplification unit is set to a correspondence of short settling time, and then the correspondence of the output voltage from the selector unit and the input of each differential pair of the differential amplification unit is controlled according to the bit information on the low-order side of the input digital signal.SELECTED DRAWING: Figure 4
机译:解决的问题:提供一种数字模拟转换电路,该数字模拟转换电路能够减少由于差分对和电压的对应引起的建立时间的变化。解决方案:数字模拟转换电路1020包括用于选择多个节点的选择器单元102D。根据数字信号的高阶位信息从分压电路输出电压,并输出差分放大单元102F,该差分放大单元102F包括输入了来自选择器单元的输出电压的多个差分对。来自选择器单元的输出电压和差分放大单元的每个差分对的输入的对应关系是根据数字信号的低阶侧上的位信息来控制的,并且输出根据数字信号的电压。当根据数字信号输出电压时,来自选择器单元的输出电压与差分放大单元的每个差分对的输入的对应关系被设置为短建立时间的对应关系,然后输出电压的对应关系被设置为来自选择器单元的信号和差分放大单元每个差分对的输入均根据输入数字信号低阶位的位信息进行控制。图4

著录项

  • 公开/公告号JP2017005408A

    专利类型

  • 公开/公告日2017-01-05

    原文格式PDF

  • 申请/专利权人 SONY CORP;

    申请/专利号JP20150115528

  • 发明设计人 AOKI TAKEYUKI;

    申请日2015-06-08

  • 分类号H03M1/68;G09G3/36;G09G3/20;G09G3/30;H03M1/76;

  • 国家 JP

  • 入库时间 2022-08-21 13:55:27

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