PROCESS DESIGN KIT FOR EFFICIENT AND ACCURATE MISMATCH SIMULATION OF ANALOG CIRCUITS

摘要

Approaches for a process design kit (PDK) for designing or manufacturing an integrated circuit with a hierarchical parameterized cell (PCELL) are provided. The PDK includes at least one model parameter which indicates a layout technique of the hierarchical PCELL, at least one hierarchical PCELL parameter which indicates at least one of the layout technique of the hierarchical PCELL and a parasitic characteristic of the hierarchical PCELL, and at least one layout vs. schematic (LVS) parameter which indicates the layout technique of the hierarchical PCELL. The hierarchical PCELL includes a pair of matching transistors. The PDK is configured to simulate and output mismatch characteristics and local variation characteristics of the hierarchical PCELL based on the at least one model parameter, the at least one hierarchical PCELL, and the at least one LVS parameter.