COMPACT MODELING ANALYSIS OF CIRCUIT LAYOUT SHAPE SECTIONS

摘要

Methodologies for compact modeling of circuit layouts to accurately account for effects of layout-induced changes in semiconductor devices induced by various intentional and unintentional mechanisms present in semiconductor processes are disclosed. The layout-sensitive compact model accounts for the impact of large layout variation on circuits by implementing techniques for obtaining the correct layout-dependent response approximations and by incorporating layout extraction techniques to obtain correct geometric parameters that drive the LDE response. In particular, these techniques include utilizing shape sections for analyzing in detail various specific region shapes of the semiconductor device. The shape sections are defined by locating vertices of each region shape and rendering reference lines at each vertex. The shape section definitions are utilized in the compact model to determine device model quantities, such as induced LDE effects upon a transistor from the region, at a finer granularity to provide for more accurate simulations.