Reduction Of Silicon Area for Ethernet PFC Protocol Implementation In Queue Based Network Processors

摘要

In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.