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Cache debug system for programmable circuits
Cache debug system for programmable circuits
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机译:可编程电路的高速缓存调试系统
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摘要
An integrated circuit may be provided with system-on-chip circuitry including system-on-chip interconnects and a microprocessor unit subsystem. The subsystem may include microprocessor cores that execute instructions stored in memory. Cache may be used to cache data for the microprocessor cores. A memory coherency control unit may be used to maintain memory coherency during operation of the microprocessor unit subsystem. The memory coherency control unit may be coupled to the system-on-chip interconnects by a bus. A command translator may be interposed in the bus. The command translator may have a slave interface that communicates with the interconnects and a master interface that communicates with the memory coherency control unit. The integrated circuit may have programmable circuitry that is programmed to implement a debug master coupled to the interconnects. During debug operations, the command translator may translate commands from the debug master.
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