首页>
外国专利>
Instruction set architecture with extended register addressing using one or more primary opcode bits
Instruction set architecture with extended register addressing using one or more primary opcode bits
展开▼
机译:指令集架构,具有使用一个或多个主要操作码位的扩展寄存器寻址
展开▼
页面导航
摘要
著录项
相似文献
摘要
A method and circuit arrangement selectively repurpose bits from a primary opcode portion of an instruction for use in decoding one or more operands for the instruction. Decode logic of a processor, for example, may be placed in a predetermined mode that decodes a primary opcode for an instruction that is different from that specified in the primary opcode portion of the instruction, and then utilize one or more bits in the primary opcode portion to decode one or more operands for the instruction. By doing so, additional space is freed up in the instruction to support a larger register file and/or additional instruction types, e.g., as specified by a secondary or extended opcode.
展开▼