Interconnection network topology for large scale high performance computing (HPC) systems

摘要

A multiprocessor computer system includes a plurality of processor nodes and at least a three-tier hierarchical network interconnecting the processor nodes. The hierarchical network includes a plurality of routers interconnected such that each router is connected to a subset of the plurality of processor nodes; the plurality of routers are arranged in a hierarchy of n≧3 tiers (T₁, . . . , T_n); the plurality of routers are partitioned into disjoint groups at the first tier T₁, the groups at tier T_i being partitioned into disjoint groups (of complete T_i groups) at the next tier T_i+1 and a top tier T_n including a single group containing all of the plurality of routers; and for all tiers 1≦i≦n, each tier-T_i−1 subgroup within a tier T_i group is connected by at least one link to all other tier-T_i−1 subgroups within the same tier T_i group.