Excess-fours processing in direct digital synthesizer implementations

摘要

Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided. Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to be responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.