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Monitoring packet residence time and correlating packet residence time to input sources

机译:监视数据包停留时间并将数据包停留时间与输入源相关联

摘要

An output circuit, included in a device, may determine counter information associated with a packet provided via an output queue managed by the output circuit. The output circuit may determine that a latency event, associated with the output queue, has occurred. The output circuit may provide the counter information and time of day information associated with the counter information. The output circuit may provide a latency event notification associated with the output queue. An input circuit, included in the device, may receive the latency event notification associated with the output queue. The input circuit may determine performance information associated with an input queue. The input queue may correspond to the output queue and may be managed by the input circuit. The input circuit may provide the performance information associated with the input queue and time of day information associated with the performance information.
机译:设备中包括的输出电路可以确定与经由由输出电路管理的输出队列提供的分组相关的计数器信息。输出电路可以确定已经发生了与输出队列相关联的等待时间事件。输出电路可以提供计数器信息和与计数器信息相关联的时刻信息。输出电路可以提供与输出队列相关联的等待时间事件通知。设备中包括的输入电路可以接收与输出队列关联的等待时间事件通知。输入电路可以确定与输入队列相关联的性能信息。输入队列可以对应于输出队列,并且可以由输入电路管理。输入电路可以提供与输入队列相关联的性能信息以及与性能信息相关联的一天中的时间信息。

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