A NONLINEAR ANALYTICAL METHOD AND SYSTEM FOR HYPERGRAPH PARTITIONING

摘要

Hypergraph partitioning is commonly used in solving VLSI placement problem, as it reduces the problem size. Hypergraph partitioning solution quality is important as the placement solution depends on the quality of cuts obtained. This paper presents a hypergraph partitioning heuristic. Here generation of IC design and fabrication of that design is obtained virtually by processing the placements of nodes between two partitions of board, by identifying efficient co-ordinates for placing nodes on the pair of partitioned boards to achieve a minimal wire length between the nodes across the partition. A memory division that stores the co-ordinates after the processing is completed and transmits these information into a super system capable of creating a design by deploying the co- ordinates and implementing the finished design by fabricating a VSLI boards based on the implemented results.