A METHOD AND DEVICE FOR DETECTION OF ERRORS AND IMPLEMENTATION OF HAMMING CODE THEORY FOR CORRECTION OF ERROR BIT IN DIGITAL DATA TRANSMISSION

摘要

The error detector circuit consists of a binary counter and generates clock pulse, when no error takes place at the receiver end. The counter produces the outputs through 0000 to 1111 and transmitted through transmission lines on to LEDs present at the receiver™s end. A set of two EX-OR and one EX-NOR gates are used at the transmitter side to function as odd parity generator i.e. when the inputs from counter to the odd parity generator are having even number of ones the parity generator will produce a logic high and logic low, if there are odd number of ones. The bits received on the receiver™s side are fed into the parity checker along with parity bit. A set of three EX-OR and one EX-NOR gates function as parity checker. The bits are checked for parity change, the parity checker produces an error signal accordingly. The error signal will be low if an odd parity is detected, indicating that transmission is error free and high if an even parity is detected, indicating an error in transmission, Then clock pulse stops to generate pulses and the function of counter is stopped. Because the NAND and EX-OR logic is used to keep the clock input to IC7493 to be low when the parity checker output is high. The hamming code analysis is used to correct the error. The parity bits, whose parity is changed are noted and those changed parity bit positions sum gives the location of erroneous bit thus obtaining the correct bit by complementing the bit present in the position obtained. This designed circuit and analysis is useful for change of one bit in transmission