首页> 外国专利> A SYSTEM FOR DECDODING OF LAW DENSITY PARITY CHECK (LDPC) ENCODED DATA

A SYSTEM FOR DECDODING OF LAW DENSITY PARITY CHECK (LDPC) ENCODED DATA

机译:一种判定法密度奇偶校验(LDPC)编码数据的系统

摘要

A semi parallel system for decoding of low density parity check (LDPC) encoded data having length L in a bit stream, 'L' being given by the function (p2s+ps+1), where p is a prime number and s is any positive integer, said system comprising, means to select a block of the bit stream of said length L, said block containing a plurality of bits; a parity check matrix having a plurality of elements; multiplication means to multiply each of said bit with said elements, to give a resultant bit-vector having plurality of bits; a plurality of parity check nodes for implementing each row of said product matrix and to update information of each bit; plurality of bit nodes adapted to receive said updated information from said parity check nodes and having means to calculate the bit probability and further adapted to transmit the calculated bit probability data to said parity check nodes; a logic control means adapted to iterate information from said parity check nodes to bit nodes until decoding is complete.
机译:半并行系统,用于解码比特流中长度为L的低密度奇偶校验(LDPC)编码数据,其中“ L”由函数(p2s + ps + 1)给出,其中p为质数,s为任意正整数,所述系统包括:选择长度为L的比特流的块的装置,所述块包含多个比特;具有多个元素的奇偶校验矩阵;乘法装置,将每个所述位与所述元素相乘,得到具有多个位的合成位向量;多个奇偶校验节点,用于实现所述乘积矩阵的每一行并更新每一比特的信息;多个比特节点,适于从所述奇偶校验节点接收所述更新的信息,并且具有计算所述比特概率的装置,并且还适于将计算出的比特概率数据发送至所述奇偶校验节点;逻辑控制装置,其适于将信息从所述奇偶校验节点迭代到比特节点,直到解码完成。

著录项

  • 公开/公告号IN277474B

    专利类型

  • 公开/公告日2016-11-25

    原文格式PDF

  • 申请/专利权人

    申请/专利号IN177/MUM/2007

  • 发明设计人 SHARMA HRISHIKESH;

    申请日2007-01-31

  • 分类号H03M13/00;

  • 国家 IN

  • 入库时间 2022-08-21 13:38:07

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