Method for asynchronous processing of digital data and the asynchronous digital system for the application of this method, preferably in the FPGA structure

摘要

in the pipelined modules (mp) is connected in the flow between at least the old main steering (ms), transposing signals (req) demands transmission and acknowledgement (ack) data for at least one of the kombinacyjnego (cl).signal transmission request (req) sent from the previous to the next module (mp), and the pipeline is full acknowledgement signal (ack) to the next to the last module pipeline is full (mp). internal input bus (mi1, mi2) data for the current system kombinacyjnego (cl) is connected to output parallel (qo) preceding module data pipeline is full (mp).the internal bus output (mo1, mo2) with data from the current system kombinacyjnego (cl1, cl2) connects with the parallel (di) of the next module, pipeline is full (mp). internal memory module in the pipeline is full (mp) recorded his output parallel (qo) data.the method is that a module potokowy (mp) applies asynchronous register potokowy apr, which he difference data for his entry in parallel (di) and remembered in the internal memory register pipeline is full apr, state his output parallel (qo) data.the current register pipeline is full correlates with signal transmission request (req) data from the previous register pipeline is full apr or acknowledgement signal (ack) of data from another register pipeline is full apr. transmission request (req) performs transfer pop for at least one external register potokowy (and _ apr1,...and _ apri) to build the similar register pipeline is full (apr). in the case wieloweju015bciowego system kombinacyjnego (cl) apply separate input registers pipelined apr11, apr12 for each in the kombinacyjnego (cl). the subject invention is also asynchronous digital system for asynchronous data processing digital way according to invention.the invention is applicable especially in the design of systems fpga.