Digital sampling circuit for a secondary clock signal to be monitored in relation to a clock fault with the help of a primary clock signal

摘要

Digital sampling circuit (100) for a secondary clock signal (204) to be monitored using a primary clock signal (202) in relation to a clock fault * with a flip-flop (102), which presents - a clock input (108), - a data input (106), - an output Q (110) and - an asynchronous reset input (112), * and with a n-bit counter (104), which presents - a clock input (114), - an asynchronous reset input (128) and - a count value output (116), the flip-flop (102) and the n-bit counter (104) electrically interconnected with each other, and in the one that * n = 2, * the primary clock signal (202) is in the clock input (114) of the n-bit counter (104), * the secondary clock signal (204) is in the input clock (108) of the flip-flop (102), * a constant signal is found in the data input (106) of the flip-flop (102), * the output Q (110) of the flip-flop (102) is connected to the input reset resistor (128) of the n-bit counter (104), characterized in that * the count value output (116) of the n-bit counter (104) is connected, via an interposed logic gate (122) and a feedback loop (130), with the asynchronous reset input (112) of the flip-flop (102) such that a reset of the n-bit counter (104) resets the flip-flop (102).