METHOD OF CONTROLLING HIGH-SPEED ACCESS TO DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY, AND DEVICE

摘要

A method of controlling high-speed access to a double data rate (DDR) synchronous dynamic random access memory (SDRAM), and a device. The method comprises: dividing, according to a dynamic allocation strategy, a DDR SDRAM into variable buffer blocks (101); and during a read or write operation with respect to the variable buffer blocks, scheduling, according to a weighted round robin strategy, a read/write operation with respect to a plurality of channels, and balancing read/write bandwidth (102).