PARALLELIZATION OF ERROR ANALYSIS CIRCUITRY FOR REDUCED POWER CONSUMPTION

摘要

A memory device (e.g., a flash memory device) includes a power efficient codeword error analysis circuit. The circuit analyzes the codewords stored in the memory of the memory device and locates and corrects errors in the codewords before the codewords are passed from the memory device to the host device requesting the codewords. The circuit includes a high parallel configuration with reduced complexity (e.g., reduced gate count) that allows the controller to perform error analysis under most circumstances. The circuit also includes a greater complexity analyzer with a lower parallel configuration that allows the controller to perform error analysis with less frequency. Since the more complex analysis part is executed less frequently, the error analysis circuit can provide significant power consumption savings compared to previous error analysis circuit designs.;