INTEGRATED CIRCUIT INCLUDING CLOCK-GATED SYNCHRONIZER FOR LOW POWER, AND DATA PROCESSING SYSTEM INCLUDING SAME

摘要

An integrated circuit is disclosed. The integrated circuit includes a delay circuit which receives and delays an asynchronous input signal; a first flip-flop which includes an input terminal connected to the output terminal of the delay circuit, a clock terminal receiving the asynchronous input signal, and a reset terminal receiving the asynchronous input signal; a synchronizer which is connected to the output terminal of the first flip-flop; and a clock-gating circuit which receives a clock signal and determines whether the clock signal is supplied to the synchronizer in response to at least one of the first output value of the delay circuit and the second output value of the first flip flop and a third output value of the synchronizer.;COPYRIGHT KIPO 2017