COMPACT AND ROBUST LEVEL SHIFTER LAYOUT DESIGN

摘要

Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. Voltage circuit or VLS that operates at different voltage levels and provides area and power savings for a multi-bit implementation of the level shifter design. Bit VLS that shifts bits from a first voltage level logic to a second voltage level logic. A VLS in which a first N-well is formed in a substrate. A second N-well formed in the substrate adjacent the side of the first N-well. And a third N-well formed in the substrate adjacent the side of the first N-well opposite the second N-well. Bit VLS circuit wherein a portion is formed in a first N-well and a portion is formed in a second N-well. Bit VLS circuit wherein a portion is formed in a first N-well and a portion is formed in a third N-well.