PROCESSOR HAVING MULTIPLE CORES SHARED CORE EXTENSION LOGIC AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS

摘要

An apparatus in an aspect includes a plurality of cores and shared core expansion logic associated with each of the plurality of cores. The shared core extension logic has shared data processing logic shared by each of the plurality of cores. The instruction execution logic is for each of the cores to call the shared core extension logic in response to the shared core extension call instruction. This call is for performing data processing by the shared data processing logic on behalf of the corresponding core. Other devices, methods, and systems are also disclosed.